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PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
FEATURES
* Six LVPECL outputs * Crystal oscillator interface * Output frequency range: 53.125MHz to 333.3333MHz * Crystal input frequency range: 25MHz to 33.333MHz * RMS phase jitter at 125MHz, using a 25MHz crystal (1.875MHz to 20MHz): 0.33ps (typical) * Full 3.3V or 3.3V core, 2.5V output supply mode * 0C to 70C ambient operating temperature * Industrial temperature information available upon request * Available in both standard and lead-free RoHS-compliant packages
Function
GENERAL DESCRIPTION
The ICS843256 is a Crystal-to-3.3V LVPECL Clock Synthesizer/Fanout Buffer designed for HiPerClockSTM Fibre Channel and Gigabit Ethernet applications and is a member of the HiperClockSTM family of High Performance Clock Solutions from ICS. The output frequency can be set using the frequency select pins and a 25MHz crystal for Ethernet frequencies, or a 19.44MHz crystal for SONET. The low phase noise characteristics of the ICS843256 make it an ideal clock for these demanding applications.
IC S
SELECT FUNCTION TABLE
Inputs FB_SEL 0 0 0 0 1 1 1 1 N_SEL1 0 0 1 1 0 0 1 1 N_SEL0 0 1 0 1 0 1 0 1 M Divide 25 25 25 25 32 32 32 32 N Divide 1 2 4 5 1 2 4 8
M/N 25 12.5 6.25 5 32 16 8 4
BLOCK DIAGRAM
Q0 nQ0 PLL_BYPASS
Pullup
PIN ASSIGNMENT
VCCO VCCO nQ2 Q2 nQ1 Q1 nQ0 Q0 PLL_BYPASS VCCA VCC FB_SEL 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 Q3 nQ3 Q4 nQ4 Q5 nQ5 N_SEL1 VEE VEE N_SEL0 XTAL_OUT XTAL_IN
Q1
1
XTAL_IN XTAL_OUT
OSC
PLL
Output Divider
nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5
0
Feedback Divider
FB_SEL N_SEL1 N_SEL0
Pulldown Pullup Pullup
ICS843256
24-Lead, 300-MIL SOIC 7.5mm x 15.33mm x 2.3mm body package M Package Top View 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm body package G Package Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
843256AM
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Type Power Output Output Output Input Power Power Input Input Input Pullup Description Output supply pins. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Selects between the PLL and cr ystal inputs as the input to the dividers. When LOW, selects PLL. When HIGH, selects XTAL_IN, XTAL_OUT. LVCMOS / LVTTL interface levels. Analog supply pin. Core supply pin. Pulldown Feedback frequency select pin. LVCMOS/LVTTL interface levels. Cr ystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output. Pullup Output frequency select pin. LVCMOS/LVTTL interface levels. Negative supply pin. Output Output Output Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels.
TABLE 1. PIN DESCRIPTIONS
Number 1, 2 3, 4 5, 6 7, 8 9 10 11 12 13, 14 15, 18 16, 17 19, 20 21, 22 23, 24 Name VCCO nQ2, Q2 nQ1, Q1 nQ0, Q0 PLL_BYPASS VCCA VCC FB_SEL XTAL_IN, XTAL_OUT N_SEL0 N_SEL1 VEE nQ5, Q5 nQ4, Q4 nQ3, Q3
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 51 51 Maximum Units pF k k
843256AM
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Function
TABLE 3. CRYSTAL FUNCTION TABLE
Inputs XTAL (MHz) 20 20 20 20 21.25 24 24 24 24 25 25 25 25 25.5 15.625 18.5625 18.75 18.75 18.75 18.75 19.44 19.44 19.44 19.44 19.53125 19.53125 19.53125 19.53125 20 FB_SEL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 N_SEL1 0 0 1 1 1 0 0 1 1 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 N_SEL0 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 1 M 25 25 25 25 25 25 25 25 25 25 25 25 25 25 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 500 500 500 500 531.25 600 600 60 0 60 0 625 625 625 625 637.5 500 594 600 600 600 600 622.08 622.08 622.08 622.08 625 625 625 625 640 VCO (MHz) N 1 2 4 5 5 1 2 4 5 1 2 4 5 4 8 8 1 2 4 8 1 2 4 8 1 2 4 8 8 Output (MHz) 500 250 125 10 0 106.25 600 300 150 12 0 625 312.5 156.25 12 5 159.375 62.5 74.25 600 300 150 75 622.08 311.04 155.52 77.76 625 312.5 156.25 78.125 80
843256AM
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
4.6V -0.5V to VCC + 0.5V 50mA 100mA 50C/W (0 lfpm) 70C/W (0 mps) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA 24 Lead SOIC 24 Lead TSSOP Storage Temperature, TSTG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical 3. 3 3.3 3. 3 TBD TBD Maximum 3.465 3.465 3.465 Units V V V mA mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = 0C TO 70C
Symbol VCC VCCA VCCO IEE ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical 3.3 3.3 2.5 TBD TBD Maximum 3.465 3.465 2.625 Units V V V mA mA
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VIH VIL IIH Parameter Input High Voltage Input Low Voltage Input High Current FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 FB_SEL PLL_BYPASS, N_SEL0, N_SEL1 VCC = VIN = 3.465V VCC = VIN = 3.465V VCC = 3.465V, VIN = 0V VCC = 3.465V, VIN = 0V -5 -150 Test Conditions Minimum 2 -0.3 Typical Maximum VCC + 0.3 0.8 150 5 Units V V A A A A
IIL
Input Low Current
843256AM
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Test Conditions Minimum VCCO - 1.4 VCCO - 2.0 0.6 Typical Maximum VCCO - 0.9 VCCO - 1.7 1. 0 Units V V V
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 3.3V5% OR 2.5V5%, TA = 0C TO 70C
Symbol VOH VOL VSWING Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter Mode of Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using an 18pF parallel resonant cr ystal. 15.625 Test Conditions Minimum Typical Maximum 25.5 50 7 1 Units MHz pF mW Fundamental
TABLE 6A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V5%, TA = 0C TO 70C
Symbol Parameter FOUT t jit(O) t sk(o) tR / tF odc Output Frequency RMS Phase Jitter (Random) Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle 20% to 80% 125MHz, Integration Range: 1.875MHz - 20MHz Test Conditions Minimum 53.125 0.33 TBD TBD 50 1 Typical Maximum 333.33 Units MHz ps ps ps % ms
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 6B. AC CHARACTERISTICS, VCC = VCCA = 3.3V5%, VCCO = 2.5V5%, TA = 0C TO 70C
Symbol Parameter FOUT t jit(O) t sk(o) tR / tF odc Output Frequency RMS Phase Jitter (Random) Output Skew; NOTE 1, 2 Output Rise/Fall Time Output Duty Cycle 20% to 80% 125MHz, Integration Range: 1.875MHz - 20MHz Test Conditions Minimum 53.125 0.32 TBD TBD 50 1 Typical Maximum 333.33 Units MHz ps ps ps % ms
PLL Lock Time tLOCK See Parameter Measurement Information section. NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential crossing points. NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
843256AM
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
TYPICAL PHASE NOISE
AT
0 -10 -20 -30 -40 -50
125MHZ @ 3.3V
Ethernet Filter
125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.33ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 10 100 1k 10k
Raw Phase Noise Data
Phase Noise Result by adding Ethernet Filter to raw data
100k
0 -10 -20 -30 -40 -50
TYPICAL PHASE NOISE
1M 10M 100M
OFFSET FREQUENCY (HZ)
AT
125MHZ @ 3.3V/2.5V
Ethernet Filter
125MHz
RMS Phase Jitter (Random) 1.875MHz to 20MHz = 0.32ps (typical)
NOISE POWER dBc Hz
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 -200 10 100 1k 10k
Raw Phase Noise Data
Phase Noise Result by adding Ethernet Filter to raw data
100k
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1M 10M 100M
REV. A NOVEMBER 29, 2005
OFFSET FREQUENCY (HZ)
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2V
2.8V0.04V 2V
VCC, VCCA, VCCO
Qx
SCOPE
VCC, VCCA
Qx VCCO
SCOPE
LVPECL
nQx V EE
LVPECL
V EE nQx
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
nQx Qx
nQ0:nQ5 Q0:Q5
t PW
nQy Qy
t
PERIOD
tsk(o)
odc =
t PW t PERIOD
x 100%
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80% Clock Outputs
80% VSW I N G
20% tR tF
20%
OUTPUT RISE/FALL TIME
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843256 provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. VCC, VCCA and VCCO should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10 resistor along with a 10F and a .01F bypass capacitor should be connected to each VCCA pin. The 10 resistor can also be replaced by a ferrite bead.
3.3V VCC .01F V CCA .01F 10F 10
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843256 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 below were determined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error.
XTAL_IN C1 18p X1 18pF Parallel Crystal XTAL_OUT C2 22p
Figure 2. CRYSTAL INPUt INTERFACE
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS INPUTS: OUTPUTS:
LVCMOS CONTROL PINS: All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k resistor can be used. LVPECL OUTPUT All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and nFOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50 transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 3A and 3B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations.
3.3V
Zo = 50 FOUT FIN
125 Zo = 50 FOUT
50 50 VCC - 2V RTT
125
Zo = 50
FIN
RTT =
1 Z ((VOH + VOL) / (VCC - 2)) - 2 o
Zo = 50 84 84
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
close to ground level. The R3 in Figure 4B can be eliminated and the termination is shown in Figure 4C.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V LVPECL driver. These terminations are equivalent to terminating 50 to VCC - 2V. For VCC = 2.5V, the VCC - 2V is very
2.5V 2.5V VCCO=2.5V R1 250 Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R2 62.5 R4 62.5 R3 250
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
R3 18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V Zo = 50 Ohm + Zo = 50 Ohm 2,5V LVPECL Driv er R1 50 R2 50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER RELIABILITY INFORMATION
TABLE 7A. JAVS. AIR FLOW TABLE FOR 24 LEAD SOIC
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 50C/W
200
43C/W
500
38C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TABLE 7B. JAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA by Velocity (Meters per Second)
0
Multi-Layer PCB, JEDEC Standard Test Boards 70C/W
1
65C/W
2.5
62C/W
TRANSISTOR COUNT
The transistor count for ICS843256 is: 3863
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
24 LEAD SOIC PACKAGE OUTLINE - G SUFFIX
FOR
PACKAGE OUTLINE - M SUFFIX
FOR
24 LEAD TSSOP
TABLE 8A. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 B C D E e H h L 10.00 0.25 0.40 0 -0.10 2.05 0.33 0.18 15.20 7.40 1.27 BASIC 10.65 0.75 1.27 8 Millimeters Minimum 24 2.65 -2.55 0.51 0.32 15.85 7.60 Maximum
TABLE 8B. PACKAGE DIMENSIONS
SYMBOL N A A1 A2 b c D E E1 e L aaa 0.45 0 -4.30 0.65 BASIC 0.75 8 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 24 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication 95, MS-013, MO-119
Reference Document: JEDEC Publication 95, MO-153
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REV. A NOVEMBER 29, 2005
PRELIMINARY
Integrated Circuit Systems, Inc.
ICS843256
FEMTOCLOCKSTM CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER
Marking TBD TBD TBD TBD Package 24 Lead SOIC 24 Lead SOIC 24 Lead "Lead-Free" SOIC 24 Lead "Lead-Free" SOIC 24 Lead TSSOP 24 Lead TSSOP 24 Lead "Lead-Free" TSSOP 24 Lead "Lead-Free" TSSOP Shipping Packaging tube 1000 tape & reel tube 1000 tape & reel tube 2500 tape & reel tube 2500 tape & reel Temperature 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C
TABLE 9. ORDERING INFORMATION
Part/Order Number ICS843256AM ICS843256AMT ICS843256AMLF ICS843256AMLFT ICS843256AG ICS843256AGT ICS843256AGLF ICS843256AGLFT
ICS843256AG ICS843256AG TBD TBD
NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843256AM
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REV. A NOVEMBER 29, 2005

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